Tool ANALYSEVHD makes static analysis of VHDL design. Currently the only feature is analysing signal dependency in VHDL design. Input XML is defined in OPTIMVHDL XML schema. Output is in format DOT - format suitable for drawing graph by application dot.
Developed by: Zdeněk Řehák
POSIX OS, Python>=2.3.
$ ./analysevhd.py file(s) file .. vhdl file
Relevant files in package VHDLVERIF:
Version 0.2 alpha
Released 28th March 2009
Version 0.1 alpha
Released 27th February 2009