VHDL Design Verification Tools


Tool ANALYSEVHD makes static analysis of VHDL design. Currently the only feature is analysing signal dependency in VHDL design. Input XML is defined in OPTIMVHDL XML schema. Output is in format DOT - format suitable for drawing graph by application dot.

Developed by: Zdeněk Řehák


POSIX OS, Python>=2.3.

NumPy library


$ ./analysevhd.py file(s)
file .. vhdl file

Relevant files in package VHDLVERIF:

  • analysevhd.py
  • common.py
  • elements.py
  • statements.py

Version history

Version 0.2 alpha

Released 28th March 2009

New features:

  • new object-oriented model
  • detection signal dependency - supported XML elements:
    • processParallelStatement
    • procedureParallelStatement
    • assignParallelStatement
    • assertParallelStatement
    • ifParallelStatement
    • forParallelStatement
    • signalAssignSequentialStatement
    • ifSequentialStatement

Version 0.1 alpha

Released 27th February 2009

New features:

  • entity ports detection
  • architecture signal detection
  • architecture component detection