VHDL Design Verification Tools


Instalation instructions and output format description are included in download packages.

Tool VHD2XML and static analysis schema are described in: Zdeněk Řehák, Translation of VHDL programs into XML intermediate-code (in czech), Master Thesis, Masaryk University, Brno, January 2009. Archived in is.muni.cz.

Abstract: Goal of the thesis was studing static analysis problems of VHDL programs, availability of commercial tools and their features. Tasks were think over own design of static analysis, implement translator from VHDL to XML code for later processing purpose, and define XML schema of translator output.