VHDL Design Verification Tools


Tool VHD2XML translates VHDL source to XML representing abstract syntactic tree. Compiler grammar is based on VHD2CA translator. Parser generator of this tool is library Python Lex-Yacc version 2.3. Output XML is defined in this XML schema.

Developed by: Zdeněk Řehák (functionality), Aleš Smrčka (compiler grammar)


POSIX OS, Python>=2.3.


$ ./vhd2xml.py file(s)
file .. vhdl file

Relevant files in package VHDLVERIF:

  • vhd2xml.py
  • lex.py*
  • yacc.py*

* files from Python Lex-Yacc library

Version history

Version 1.1 beta

Released 29th October 2008

New features:

  • multiple file arguments
  • xml schema validation tags

Bug fix:

  • id & object elements (many changes of grammar and xml schema):
    • constant, variable, signal and file declaration
    • type identifier
    • object, record, aggregate expression
    • procedure, function call
    • signal, variable assignment
  • declaration semicolon duplicate
  • missing optional declaration list in function and procedure declaration
  • incomplete use clause

Version 1.0 beta

Released 1st October 2008

New features:

  • first release (full functionality)