VHDL Design Verification Tools
Tool VHD2XMLTool VHD2XML translates VHDL source to XML representing abstract syntactic tree. Compiler grammar is based on VHD2CA translator. Parser generator of this tool is library Python Lex-Yacc version 2.3. Output XML is defined in this XML schema. Developed by: Zdeněk Řehák (functionality), Aleš Smrčka (compiler grammar) RequirementsPOSIX OS, Python>=2.3. Usage$ ./vhd2xml.py file(s) file .. vhdl file Relevant files in package VHDLVERIF:
* files from Python Lex-Yacc library Version historyVersion 1.1 betaReleased 29th October 2008 New features:
Bug fix:
Version 1.0 betaReleased 1st October 2008 New features:
|